module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
	
	localparam IDLE =4'h0;
	localparam S1 =4'h1;
	localparam S2 =4'h2;
	localparam S3 =4'h3;
	localparam S4 =4'h4;
	localparam S5 =4'h5;
	localparam S6 =4'h6;
	localparam S7 =4'h7;
	localparam S8 =4'h8;
	localparam S9 =4'h9;
	
	reg [3:0]state;
	reg [3:0]next_state;
	reg [2:0]out_r;
	always@(posedge clk)begin
		if(reset)begin
			state<=IDLE;
		end
		else begin
			state<=next_state;
		end
	end
	
	always@(*)begin
		case(state)
			IDLE:begin out_r=3'b000;next_state=(in)?S1:IDLE; end//0*****
			S1:begin out_r=3'b000;next_state=(in)?S2:IDLE; end//01*****
			S2:begin out_r=3'b000;next_state=(in)?S3:IDLE; end//011****
			S3:begin out_r=3'b000;next_state=(in)?S4:IDLE; end//0111***
			S4:begin out_r=3'b000;next_state=(in)?S5:IDLE; end//01111**
			S5:begin out_r=3'b000;next_state=(in)?S7:S6; end//011111*
			S6:begin out_r=3'b100;next_state=(in)?S1:IDLE; end//0111110
			S7:begin out_r=3'b000;next_state=(in)?S8:S9; end//0111111*
			S8:begin out_r=3'b001;next_state=(in)?S8:IDLE; end//01111111
			S9:begin out_r=3'b010;next_state=(in)?S1:IDLE; end//01111110
		endcase
	end
	assign disc=out_r[2];
    assign flag=out_r[1];
    assign err=out_r[0];
endmodule